Integrated circuit with a strongly-conductive buried layer

ABSTRACT

An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of semiconductorintegrated circuits. More specifically, the present invention relates toimproving the conductivity of a buried layer.

[0003] The present invention will more specifically be described in thecontext of the forming of a buried collector layer of a bipolartransistor, but those skilled in the art will realize from reading thepresent application and as underlined at the end of the presentdescription, that the present invention applies generally to theformation of deep strongly-conductive layers in a semiconductorsubstrate.

[0004] 2. Discussion of the Related Art

[0005]FIG. 1 very schematically shows a bipolar transistor structureformed in a semiconductor substrate. This bipolar transistor is, in thespecific described embodiment, formed in an N-type layer 1 formed byepitaxy on a P-type substrate 2. Under the active area where thetransistor is to be formed, an implantation intended to form aheavily-doped N-type buried layer 3 will have been formed, generallyprior to the epitaxy. The active transistor area is laterally delimitedby a silicon oxide well 5 etched into the surface of epitaxial layer 1,currently designated as an STI, for Shallow Trench Insulation. Inside ofthe active area are formed a P-type base region 7 and an N-type emitterregion 8. Many methods are known to form such regions in properlylocalized fashion and to take contacts on these regions. Reference will,for example, be made to U.S. Pat. No. 5,953,600 which is incorporatedherein by reference. The transistor collector is formed of a portion ofepitaxial layer I and of an area 9 also of type N implanted opposite tothe emitter. The collector is contacted by an N⁺-type buried layer 3 andby an N⁺-type conductive well 10 crossing the insulating well 5 andjoining the buried layer 3.

[0006] When such a transistor is to be operated at a high frequency, oneof the main limiting parameters appears to be the collector accessresistance, that is, the sum of lateral resistance R1 of buried layer 3and of vertical resistance R2 of collector well 10.

[0007] Various solutions are known to minimize the resistance ofcollector well 10, by strongly increasing the doping level, by reducingits height, or by forming an opening and filling it with polysiliconand/or other strongly-conductive materials. Thus, the main element ofthe collector access resistance remains resistance R1 of buried layer 3.Further, the doping of this layer cannot be increased to a maximum,especially since it exhibits risks of exodiffusion to the epitaxiallayer and of creation of a ghost layer during epitaxy.

[0008] It should further be noted that buried layer 3 has a dualfunction. On the one hand, it ensures a contact with collector region 1,9, and on the other hand, it is of a conductivity type opposite to thatof the substrate on which the epitaxial layer is formed, to ensure ajunction isolation and enable proper biasing of the substrate.

SUMMARY OF THE INVENTION

[0009] An object of the present invention is to increase theconductivity of a buried layer while maintaining its double function ofcontact and junction isolation with respect to the substrate.

[0010] Another object of the present invention is to provide variousmethods to obtain such a buried layer with an improved conductivity.

[0011] Another more specific object of the present invention is to formthe buried collector layer and the associated contact for a bipolartransistor.

[0012] To achieve these and other objects, the present inventionprovides an integrated circuit comprising a buried layer of determinedconductivity type in a plane substantially parallel to the plane of amain circuit surface, in which the median portion of this buried layeris filled with a metal-type material.

[0013] According to an embodiment of the present invention, the buriedlayer is a sub-collector layer of a bipolar transistor.

[0014] According to an embodiment of the present invention, themetal-type material is titanium nitride.

[0015] The present invention also provides a method for forming a buriedlayer in a semiconductor substrate of an integrated circuit, comprisingthe steps of providing, at the location where the buried layer isdesired to be formed, a layer portion made of a material selectivelyetchable with respect to the rest of the semiconductor material, dopingthe semiconductor substrate according to a selected conductivity type oneither side of said layer portion, digging an opening extending from theintegrated circuit surface to said layer portion, removing said layerportion by isotropic etch, and filling the cavity thus formed with ametal-type material.

[0016] According to an embodiment of the present invention, the layerportion is delimited by an insulating wall.

[0017] According to an embodiment of the present invention, the layerportion is a silicon-germanium region formed by epitaxy on a siliconsubstrate and itself covered with a silicon epitaxial layer.

[0018] According to an embodiment of the present invention, the layerportion is a silicon oxide region, formed on a silicon substrate andcoated with a silicon layer.

[0019] According to an embodiment of the present invention, the layerportion is a hollowed region formed in advance in the semiconductorsubstrate.

[0020] The foregoing objects, features and advantages of the presentinvention will be discussed in detail in the following non-limitingdescription of specific embodiments in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1, previously described, is a simplified cross-section viewof a bipolar transistor according to the state of the art;

[0022]FIG. 2 is a simplified cross-section view of a bipolar transistorprovided with a buried layer according to the present invention;

[0023]FIGS. 3A to 3D are cross-section views illustrating successivesteps of a first manufacturing mode of a transistor according to thepresent invention;

[0024]FIGS. 4A to 4C are cross-section views illustrating successivesteps of a second manufacturing mode of a transistor according to thepresent invention; and

[0025]FIGS. 5A and 5B are cross-section views illustrating successivesteps of a third embodiment of a transistor according to the presentinvention.

DETAILED DESCRIPTION

[0026]FIG. 2 shows a bipolar transistor comprising a modified buriedlayer according to the present invention. Buried layer 3 is replacedwith a buried layer 13 having as its periphery 14, like buried layer 3of FIG. 1, a heavily-doped silicon layer of the desired conductivitytype. However, the core of this buried layer is replaced with astrongly-conductive layer 15, preferably a metal-type layer. Collectorwell 10 is preferably filled with the same material 15 as that formingthe core of buried layer 13. The conductive material is for examplecopper deposited by electrochemical deposition or any otherstrongly-conductive material adapted to filling a cavity such as aconductive oxide, a metal silicide, or a titanium or tantalum nitride,or another material exhibiting the same features. Material 15 may alsocomprise at its periphery a metal, or another strongly-conductivematerial such as a nitride or a silicide, and have a core of anothernature, for example, polysilicon or even silicon oxide.

[0027] According to the present invention, given that most of theconductivity of the buried layer is ensured by metal core 15, peripheralheavily-doped area 14 may be less heavily doped than buried layer 3 ofprior art. Indeed, it is enough for this layer to exhibit a good ohmiccontact with metal core 15. Risks of exodiffusion to the upper epitaxiallayer during epitaxy and of creation of a ghost layer are thus limited.

[0028] The forming of epitaxial layers with metal-type cores accordingto the present invention enables reducing, by a factor of at least 10,the value of resistance R1 exhibited in relation with FIG. 1, andenables reducing the doping of peripheral region 14, which simplifiesthe manufacturing. Especially, if peripheral region 14 is less heavilydoped than in prior art, the size of the extension of the doped regionduring anneals decreases, which further improves the device.

[0029] Three embodiments of a buried layer according to the presentinvention will now be described as examples only.

EXAMPLE 1

[0030] Substrate Comprising an SiGe Layer

[0031]FIGS. 3A to 3D illustrate four successive steps of a first exampleof manufacturing of a buried layer according to the present invention.

[0032] As illustrated in FIG. 3A, the process starts from a P-typesilicon substrate 20 on which a silicon-germanium layer (SiGe) 21 hasbeen formed by epitaxy. On layer 21 is formed by epitaxy an N-typesilicon layer 22. At least the portion which will correspond to theactive area of the component which is desired to be manufactured issurrounded with N⁺ regions 23 and 24. This can, for example, be obtainedby heavily doping the SiGe during its epitaxial growth, the N⁺ regionthen forming by diffusion in the silicon during the subsequent thermalsteps. An implantation after growth of the SiGe, or a deep implantationafter forming of epitaxial layer 22, may also be performed. Theseimplantations are preferably localized, only under the active region.Preferably still, a heavily-doped N-type layer, a germanium-siliconlayer, a heavily-doped N-type silicon layer, and a lightly-doped N-typelayer may be successively grown; the use of successive epitaxiesespecially enables reducing anneals.

[0033] Then, as illustrated in FIG. 3B, the usual steps of the formingof a bipolar transistor, similar to those mentioned in relation withFIG. 1, are also carried out. However, in this case, a deep insulatingwall, deeper than SiGe layer 21, designated by reference numeral 26, hasalso been formed in addition to shallow insulating well 5. A firstadvantage of such an insulating wall is to avoid, for heavily-dopedN-type regions, laterally diffusing towards neighboring components inthe various anneals. The insulating walls are not necessarily completelyfilled with an insulator, but possibly only their outer walls are coatedwith an insulator, the rest being filled with polysilicon, which isoften easier to deposit. The same elements as those described inrelation with FIG. 1 are then formed, that is, the layers and base andemitter contacts 7 and 8, and possibly a collector implantation 9.

[0034] At the step illustrated in FIG. 3C, an opening 28 is made in well5, this opening extending to join SiGe layer 21. It should be noted thatin practice, there generally exist upper insulating layers above thestructure, resulting from the emitter and base region manufacturingprocesses. Thus, opening 28 will also cross these insulating layers notshown. Opening 28 has been shown as slightly penetrating into the SiGelayer. In practice, a first vertical anisotropic etch of well 5 followedby a second vertical anisotropic etch of the silicon of epitaxial layer22 will be performed, to reach SiGe region 21.

[0035] At the step illustrated in FIG. 3D, an isotropic etch by aproduct selectively etching the SiGe is performed to completely removethe portion of SiGe layer delimited by wall 26 and form a cavity at thelocation which was taken up by this layer portion. Isotropic SiGe plasmaetch methods are known, which exhibit a selectivity greater than 30between the SiGe etching and the silicon and silicon oxide etching.Finally, titanium nitride (TiN) 29 which fills the cavity thus createdor at least coats its internal walls is finally deposited by chemicalvapor deposition (CVD), or by atomic deposition processes currentlycalled ALD in the art. Normally, an almost complete filling by TiN 29appears to have been performed, as shown in FIG. 3D. For this filling,one of the other previously-mentioned conductive materials could also beused.

EXAMPLE 2

[0036] SOI-Type Substrate

[0037]FIGS. 4A to 4C illustrate successive steps of a second example ofmanufacturing of a buried layer according to the present invention.

[0038] As illustrated in FIG. 4A, the process starts from an SOI-typestructure, comprising a substrate 30, for example of P-type silicon, asilicon oxide layer 31, and an epitaxial lightly-doped N-type siliconlayer 32. Oxide layer 31 is surrounded with heavily-doped N-type regions33 and 34 obtained by any known method, as indicated previously.Possibly, in an SOI-type structure obtained by assembly of two siliconwafers, these heavily-doped N-type regions may be formed beforeassembling the two wafers intended to form the structure.

[0039] Then, steps similar to those described in relation with FIG. 3Bare carried out to obtain the structure shown in FIG. 4B.

[0040] After this, as illustrated in FIG. 4C, an opening 38 is formed,which extends to reach silicon oxide layer 31. Preferably, as shown inFIG. 4B, the region where opening 38 will be formed is a reservedsilicon portion inside of oxide well 5. Then, as illustrated in FIG. 4C,opening 38 does not reach the edges of well 5 but is entirely formed inthe silicon. This has the advantage that, at the next step during whichthe silicon oxide layer portion 21 delimited by wall 26 is etched, thewalls of well 5 are not simultaneously etched. In this case also, deepperipheral walls 26 will preferably exhibit an outer surface coated withsilicon nitride to avoid etching of these walls at the same time as ofSiO₂ region 31. In a last phase, opening 38 and the cavity provided inthe layer portion of SiO₂ delimited by walls 26 are filled with aconductive material, as described in the context of the first example.

EXAMPLE 3

[0041] Substrate with a Pre-Formed Cavity

[0042] A silicon structure comprising in a substrate 40 a cavity 41 mayalso be used, as shown in FIG. 5A. Such a cavity 41 may be formed byetching into the upper substrate surface close narrow grooves and byperforming a high-temperature anneal. A cavity then forms substantiallyat the location of the groove bottom and the upper silicon surfaceobturates again. Doping processings are then performed so that layer 42above the cavity is lightly N-type doped if the substrate is P-typedoped.

[0043] Then, a heavily-doped N-type region is formed on either side ofthe cavity and the process carries on in the same way as describedpreviously by first forming the elements of a transistor, then boring anopening 48 which will join cavity 41. This cavity is then filled, forexample, by TiN as described previously. To form the heavily-doped Nregions around the cavity, it is possible, prior to the cavity filing,to diffuse an N-type doping, for example, from polysilicon.

[0044] Of course, the present invention is likely to have variousalterations, modifications, and improvements which will readily occur tothose skilled in the art, especially as concerns the choice of thefilling materials and the etch modes. The basic idea of the presentinvention is to create an inhomogeneous layer portion with respect tothe polysilicon at the location where a buried layer is desired to beformed and, after having formed a port to this inhomogeneous region, tore-etch this region to form a void therein, which is then filled with avery conductive material. In the context of the first two manufacturingexamples, the layer portion is a portion of a continuous layer delimitedby a continuous peripheral wall. It could also be provided that, beforeepitaxy of the upper layer, a layer portion having the desired contour,for example, a basin, etched in the substrate, is directly formed.

[0045] Further, the present invention has been described only in thecontext of the forming of the collector of an NPN-type transistor. Itwill of course apply to the forming of a collector of a PNP-type bipolartransistor. It will more generally apply to the forming of a buriedlayer with a very high conductivity level everywhere such a layer may beuseful. The present invention especially applies in the context ofsubmicronic structures in which, for example, the active surface areadelimited by deep insulating wall 26 has a dimension on the order of0.8×1.4 μm² and in which the layer thicknesses have values on the orderof one tenth of a micrometer.

[0046] It should also be noted that the buried layer according to thepresent invention is not only a good electric conductor, but also a goodheat conductor. Thus, a specific advantage of the present invention isthat the heat dissipation of the device arranged above the buried layeris improved. The upper structure of the collector well may be optimizedto improve this heat dissipation.

[0047] Such alterations, modifications, and improvements are intended tobe part of this disclosure, and are intended to be within the spirit andthe scope of the present invention. Accordingly, the foregoingdescription is by way of example only and is not intended to belimiting. The present invention is limited only as defined in thefollowing claims and the equivalents thereto.

What is claimed is:
 1. An integrated circuit comprising a buried layerof determined conductivity type in a plane substantially parallel to theplane of a main circuit surface, wherein a median portion of said buriedlayer is filled with a metal-type material.
 2. The integrated circuit ofclaim 1, wherein the buried layer is a sub-collector layer of a bipolartransistor.
 3. The integrated circuit of claim 1, wherein the metal-typematerial is titanium nitride.
 4. A method for forming a buried layer ina semiconductor substrate of an integrated circuit, comprising the stepsof: providing, at the location where the buried layer is to be formed, alayer portion made of a material selectively etchable with respect tothe rest of the semiconductor material, doping the semiconductorsubstrate according to a chosen conductivity type on either side of saidlayer portion, digging an opening extending from the integrated circuitsurface to said layer portion, removing said layer portion by isotropicetch, and filling the cavity thus formed with a metal-type material. 5.The method of claim 4, wherein the layer portion is delimited by aninsulating wall.
 6. The method of claim 4, wherein the layer portion isa silicon-germanium region formed by epitaxy on a silicon substrate anditself covered with a silicon epitaxial layer.
 7. The method of claim 4,wherein the layer portion is a silicon oxide region, formed on a siliconsubstrate and coated with a silicon layer.
 8. The method of claim 4,wherein the layer portion is a hollowed region formed in advance in thesemiconductor substrate.